Mastering Controlled Area Networks (CAN): A Comprehensive Overview

CAN is a popular robust standard designed to communicate between the micro-controller without any help of a computer in the automotive domain. This was developed by Bosch in 1980. But now this is used in many other areas like industrial automation, medical equipment etc.

Every microcontroller or entity that is supposed to send or receive data from others is called a node.

The CAN bus is a broadcast-type bus, meaning there is no way to send a message to a particular node; all nodes can ‘hear’ all the messages. However, the CAN hardware supports a filtering mechanism to select the messages it is interested in.

CAN follows Non-Return-to-Zero (NRZ) encoding, meaning the signal level does not return to zero between bits. Instead, the signal stays at the same level (high or low) for the entire bit duration, which allows for efficient use of bandwidth and helps in maintaining signal integrity over longer distances.

BIT representation in CAN – Dominant and Recessive bits

The CAN bus typically uses a twisted pair of wires, named CAN_L and CAN_H. The logic level on the bus is determined by the voltage difference between these two wires. When CAN_H is pulled to around 3.5v and CAN_L is around 1.5v, the voltage difference is approximately 2v. This bus state is interpreted as a logic 0 or dominant bit. You may wonder why the logic 0 becomes dominant…!! The term “dominant” is derived from its behavior during arbitration and collision detection.

When CAN_H and CAN_L are both at the same voltage (2.5v), the voltage difference is 0. This state is called a logic 1 or recessive bit. Since the communication relies on the voltage difference between the wires, CAN bus communication is more tolerant to external noise. For example, if the wires pass through a magnetic field, any induced voltage will affect both wires equally. Because the system measures the difference between the voltages on the two wires, these noise effects cancel each other out.

Message Identifiers

In CAN protocol the messages will have an identifier rather than nodes as in I2C. The identifier would be encapsulated inside the messages and which will decide the priority of the message. The smaller value of the identifier will have higher priority.

There are two types of identifiers

Standard identifier – This is 11 bit length and used in the classical CAN protocol (CAN2.0A)
Extended identifier – This is 29 bit width and used in CAN2.0B

Arbitration for CAN bus

To ensure that messages are transmitted in an orderly manner without collisions, even when multiple nodes attempt to communicate simultaneously, arbitration is used to determine which node can use the CAN bus at a given time. The arbitration will be done by comparing bit by bit from left to right. The dominant bit (logic 0) will alway override the recessive bit (logic 1). So any message whose identifier transmitted over the bus without seeing any discrepancy will win the arbitration.

Eg. Node A sends a message with identifier 1001010

Node B sends a message with identifier 1001101

In the above case the 5th bit from MSB is dominant in Node A but it’s recessive in Node B. So Node A will win the arbitration. When two nodes send the same identifier resulting in a bit error and destruction of the message.

Time Quanta (tq)

Suppose a microcontroller operates at a particular clock frequency (system frequency). This clock frequency may be multiplied or divided by some factor to produce a resulting clock for the CAN controller. This resulting clock is then divided by a prescaler to obtain a new clock. The time period of this new clock is called a time quanta (TQ). In other words, the time quanta is the basic unit of time used to define the different segments of a bit in CAN communication.

Bit Segments

Each bit in CAN communication is divided into four segments, as depicted in the following diagram.

Synchronization Segment (SYNC_SEG) – This is a segment where the edges of each bit are expected to occur. The width of this segment will be always fixed (1 tq).
Propagation Segment – Used to compensate for the physical delay within the network. The delay includes the propagation delay to reach data at destination as well as the internal delay of the CAN node.
Phase Segment 1 – May be lengthened temporarily by synchronization
Phase Segment 2 – May be shortened temporarily by synchronization

NB: The bit sampling will occur anywhere in the Phase segment 1 & 2. So if there are two nodes in the network (say A-local and B-remote), the bit sent by B should reach A before the phase segment starts. This is the criteria to define the width of the propagation segment.

tq – Time Quanta

T_AB– Time delay between node A to B (Output delay of A + channel delay + Input delay of B)

T_BA– Time delay between node B to A (Output delay of B + channel delay + Input delay of A)

Sampling will occur any time in T_SAMP. So the remote node bit should reach before the phase segment starts.

Assuming the T_AB and T_BA are equal, the propagation delay should be greater than (T_AB + T_BA)

Eg. Consider the arbitration for CAN bus, Suppose Node B is sending the dominant bit (logic 0) and Node A sending the recessive bit(logic 1). In the diagram below, the propagation segment has enough width so it will compensate for the delay between A and B.

Node A has a recessive bit (logic 1). This will set bus logic to a high state. After a time period of T_AB, Node B sets the bus logic 0 corresponding to its dominant bit. This change would be reflected in Node A after the time T_BA. But node A is still in the propagation delay segment. Since the sampling occurs during the phase segment, the Node A will lose the arbitration since node A detects logic 0 in the bus rather than logic 1.

At the same time, node B detects that the bus is logic 0 during its sampling time, and node B wins the arbitration.

In the above diagram, the propagation delay is shorter, so the sampling in node A may happen even before the Node B sets the dominant bit in the bus. In this case the Node A will think that he has won the arbitration. When B sets the dominant bit in the bus, B also thinks that he has won the arbitration, resulting in the error condition and destruction of the frame.

Phase Segments & Synchronization

In order to control the distance between the edge of the bit and the sampling point the bits between the nodes should be synchronized. The synchronization between them will happen during the recessive to dominant transition(Falling Edge). An edge of a received bit is synchronous if it comes inside the synchronization segment of the current node’s bit.

There are two types of synchronizations

1. Hard Synchronization – All CAN nodes are internally hard synchronized to the falling edge of the Start of frame (SOF) bit detected on the bus. Hard synchronization is performed during bus idle.

2. Bit resynchronization – This is achieved by lengthening and shortening the width of phase segments. If the phase error is positive, the phase segment 1 will be lengthened. If the error is negative, the phase segment 2 will be shortened.

Edge Phase Error

If the edge of the received bit does not fall under the synchronization segment, The distance between the edge and end of the sync segment is called edge phase error. If the edge comes before the sync segment, that is negative edge phase error, if the edge is after sync segment it’s positive phase error.

(Re-)Synchronization Jump Width (SJW)

For bit resynchronization, either we will need to lengthen the phase segment 1 or shorten the phase segment 2. But we cannot change this value as much as we need. In order to limit the value we need to program the SJW parameter (in terms of time quanta). If the phase error is greater than the SJW value, the lengthening or shortening should be done by the amount of SJW. Otherwise change by the amount of phase error.

Let us examine the positive edge phase error and negative edge phase error with the following sample frame.

Example for Late Edge (Positive Edge Phase Error) Synchronization

In the above example, the edge of the incoming stream bit came at the end of the propagation segment (Late Edge). So the phase segment 1 lengthened by 4 time-quanta to delay the sampling point.

Example for Early Edge (Negative Edge Phase Error) Synchronization

In the above example, the Edge of bit came earlier than the sync segment during the phase segment 2 of the previous bit. So the phase segment 2 has been reduced by 1 time-quanta and removed the next sync segment. Thus the sampling time again becomes the same as it would have been from sync bit if there is bit edge error.

Bit Stuffing

In order to maintain the proper synchronization between the CAN nodes, it is necessary to have enough edges (bit transition between dominant and recessive) in the frame. But if we are sending data with all dominant or all recessive, there is a high chance to lose the synchronization. To avoid this problem the Bit stuffing is used. By using this method if the frame has 5 consecutive bits that have similar polarity, an opposite polarity bit will be added after that.

e.g. 1111100001111000000 → 11111000001111100000100

Red colored bits are stuffed bits.

CAN Frame

Now that we understand how a single bit is used in the CAN bus, the next step is to understand what a CAN frame looks like.

The CAN frame has different parts as depicted in the diagram below. Each segment is composed of several bits, with each bit in the frame carrying its own specific meaning.

There are two message frame format

Base frame format – uses 11 bit address as message identifier
Extended frame format – uses 29 bit addresses as message identifier

Base Frame Format

Start Of Frame (SOF) – 1 bit – This bit indicates the start of a new frame. In idle case the bus would be logic high (recessive state). When a node has to send a message, the bus pulls to logic low (dominant state) to indicate the start of frame (SOF).
Identifier – 11 bits – A unique identifier of the message. Also set priority of a CAN message.
Reserved – 2 bits
Data Length Code (DLC) – 4 bits – A 4 bit data which shows the length of data in bytes encapsulated in the frame.
Data – 0-64 bits – The actual data.
Cyclic Redundancy Check (CRC) – 15 bits – The cyclic redundancy check code for error detection
CRC Delimiter bit (CRCD) – 1 bit – Must be recessive bit
ACK Field – 2 bits – Transmitter send a recessive bit, any receiver can assert a dominant bit
End of Frame (EOF) – 7 bits – Must be recessive
Inter Frame Spacing (IFS) – 3 bits – Must be recessive

Extended Frame Format

In this format, every field is the same as that of the base frame format, except SRR, Second part of identifier, RTR.

Substitute Remote Request (SRR) – 1 bit – Must be recessive
Identifier second part – 18 bits – Second part of identifier, which also determine the message priority
Remote Transmission Request (RTR) – 1 bit – Must be dominant for data frame and recessive for remote request frame.

Bus Connections

CAN bus uses twisted pair wiring consists of a pair of wires twisted together to form the CAN_H and CAN_L lines, which carry differential signals between nodes, thereby reducing the impact of electromagnetic interference (EMI). This setup typically uses a twisted pair cable with a 120-ohm characteristic impedance. To prevent signal reflections and ensure proper operation of differential signal transmission, termination resistors are placed at both ends of the CAN bus. These resistors, each with a value of 120 ohms, are connected between CAN_H and CAN_L at both ends of the bus. Additionally, a power supply is required to provide the necessary operating voltage, typically 3.3V or 5V, to the microcontroller, CAN transceiver, and other components in the CAN bus system.